From 410a868f79165d6d2559bc8508ba496450fbe1ee Mon Sep 17 00:00:00 2001 From: Nick McKinney Date: Thu, 29 Dec 2016 15:54:36 -0600 Subject: widen register set control signal, fix bugs with conditional sets related to branching --- nqcpu.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'nqcpu.v') diff --git a/nqcpu.v b/nqcpu.v index 9dac5cf..9696302 100644 --- a/nqcpu.v +++ b/nqcpu.v @@ -19,7 +19,7 @@ module nqcpu ( output debugMemWriteB, output debugMemWriteW, - output [4:0] debugSetRegCond, // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this} + output [5:0] debugSetRegCond, // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this} output [15:0] dbg_r0, output [15:0] dbg_r1, @@ -58,7 +58,7 @@ module nqcpu ( end end - wire [31:0] ctrl_from_decoder; + wire [32:0] ctrl_from_decoder; wire [15:0] imm_from_decoder; wire [15:0] pc_from_decoder; @@ -103,7 +103,7 @@ module nqcpu ( .dbg_r7(dbg_r7) ); - wire [31:0] ctrl_from_alu; + wire [32:0] ctrl_from_alu; wire [15:0] imm_from_alu; wire [15:0] pc_from_alu; alu_stage alu_inst ( -- cgit v1.2.3