diff options
Diffstat (limited to 'alu_stage.v')
| -rw-r--r-- | alu_stage.v | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/alu_stage.v b/alu_stage.v index 7bdbfe8..b178cad 100644 --- a/alu_stage.v +++ b/alu_stage.v @@ -15,15 +15,15 @@ module alu_stage ( output rf_lb, input [15:0] rf_dataA, input [15:0] rf_dataB, - + // memory interface input [15:0] memData_in, // read in from memory output reg [15:0] memData_out, // to write out to memory - + // setting PC output setPC, output [15:0] setPCValue, - + output reg [32:0] control_signals_out, output reg [15:0] imm_out, output reg [15:0] pc_out, @@ -77,7 +77,7 @@ module alu_stage ( aluOpSource1_in == 2'h0 ? rf_dataA : aluOpSource1_in == 2'h1 ? memData_in : aluOpSource1_in == 2'h2 ? {imm_in} : pc_in; - + wire [15:0] aluSrc2; assign aluSrc2 = aluOpSource1_in == 2'h0 ? rf_dataB : @@ -93,7 +93,7 @@ module alu_stage ( .zero(aluZero), .carry(aluCarry) ); - + wire setRegZCond, setRegCCond, setSomeReg; assign setRegZCond = setRegCond_in[4] | (setRegCond_in[3] == statusReg[1]); assign setRegCCond = setRegCond_in[1] | (setRegCond_in[0] == statusReg[0]); @@ -116,7 +116,7 @@ module alu_stage ( assign setPC = setSomeReg & aluDest_in; assign setPCValue = aluResult; - + always @(posedge clk) begin if(en) begin control_signals_out <= control_signals_in; @@ -126,7 +126,7 @@ module alu_stage ( statusReg <= {aluZero, aluCarry}; // not quite right; should only happen for a few instructions end end - + assign dbg_statusreg = statusReg; endmodule |