From 5d3e120708eaf41ddad4ce9fd049a95b0577e399 Mon Sep 17 00:00:00 2001 From: Nick McKinney Date: Thu, 29 Dec 2016 21:30:17 -0600 Subject: add timing constraints file --- nqcpu.sdc | 107 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 nqcpu.sdc diff --git a/nqcpu.sdc b/nqcpu.sdc new file mode 100644 index 0000000..d39483b --- /dev/null +++ b/nqcpu.sdc @@ -0,0 +1,107 @@ +## Generated SDC file "soc.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" + +## DATE "Thu Dec 29 19:30:14 2016" + +## +## DEVICE "EP2C20F484C7" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clk} -period 50.000 -waveform { 0.000 10.000 } [get_ports {clk}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + -- cgit v1.2.3