From 7a8184a7c5b1e15c8c3446feb3a927b0fc347242 Mon Sep 17 00:00:00 2001 From: Nick McKinney Date: Thu, 29 Dec 2016 15:56:51 -0600 Subject: add simplistic status register and associated debug lines --- alu_stage.v | 8 +++++++- nqcpu.v | 8 ++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/alu_stage.v b/alu_stage.v index e070e4e..3761f25 100644 --- a/alu_stage.v +++ b/alu_stage.v @@ -22,8 +22,11 @@ module alu_stage ( output reg [32:0] control_signals_out, output reg [15:0] imm_out, - output reg [15:0] pc_out + output reg [15:0] pc_out, + + output [1:0] dbg_statusreg ); + reg [1:0] statusReg; // decode signals wire [3:0] aluOp_in; @@ -101,7 +104,10 @@ module alu_stage ( imm_out <= imm_in; memData_out <= aluResult; pc_out <= pc_in; + statusReg <= {aluZero, aluCarry}; // not quite right; should only happen for a few instructions end end + + assign dbg_statusreg = statusReg; endmodule diff --git a/nqcpu.v b/nqcpu.v index 9696302..34935c6 100644 --- a/nqcpu.v +++ b/nqcpu.v @@ -29,7 +29,9 @@ module nqcpu ( output [15:0] dbg_r5, output [15:0] dbg_r6, output [15:0] dbg_r7, - output [9:0] dbg_state + output [9:0] dbg_state, + + output [1:0] dbg_statusreg ); reg [15:0] pc; @@ -130,7 +132,9 @@ module nqcpu ( .control_signals_out(ctrl_from_alu), .imm_out(imm_from_alu), - .pc_out(pc_from_alu) + .pc_out(pc_from_alu), + + .dbg_statusreg(dbg_statusreg) ); control_unit control_unit_inst ( -- cgit v1.2.3