From f8d09347a43ddab462d94f716e0a6f249e2e6635 Mon Sep 17 00:00:00 2001
From: Bobby Bingham <koorogi@koorogi.info>
Date: Sun, 8 Jan 2017 15:09:38 -0600
Subject: Move ALU test cases to external testcase file

This makes is a little easier to create new ALU testcases and to quickly
read and understand the existing testcases.  Additionally, the test bench
itself can now report when a test fails, rather than requiring inspection
on the waveform (though the waveform is still available).
---
 Makefile     |  4 ++--
 alu_tb.v     | 74 +++++++++++++++++++++++-------------------------------------
 testbench.vh | 27 ++++++++++++++++++++++
 tests/alu    | 19 ++++++++++++++++
 4 files changed, 76 insertions(+), 48 deletions(-)
 create mode 100644 testbench.vh
 create mode 100644 tests/alu

diff --git a/Makefile b/Makefile
index 12b015b..55be36b 100644
--- a/Makefile
+++ b/Makefile
@@ -24,8 +24,8 @@ clean:
 
 .SECONDEXPANSION:
 pc := %
-%_tb.sim: %_tb.v %.v $$(patsubst $$(pc),$$(pc).v,$$(DEPS-$$*))
-	$(IV) $(IVFLAGS) -o $@ $^
+%_tb.sim: %_tb.v %.v testbench.vh $$(patsubst $$(pc),$$(pc).v,$$(DEPS-$$*))
+	$(IV) $(IVFLAGS) -o $@ $(filter-out %.vh,$^)
 
 .PHONY: all simulate clean
 .SECONDARY:
diff --git a/alu_tb.v b/alu_tb.v
index 6afafbc..8342e6c 100644
--- a/alu_tb.v
+++ b/alu_tb.v
@@ -1,3 +1,4 @@
+`include "testbench.vh"
 `timescale 1 ns / 100 ps
 
 module alu_tb ();
@@ -11,58 +12,39 @@ module alu_tb ();
 	wire carry;
 	reg expected_carry;
 
+	reg [3*8:0] opstr;
+	integer file, r;
+
 	initial begin
 		$dumpfile("alu_tb.vcd");
 		$dumpvars(0, alu_tb);
 
-		x = 16'h0123;
-		y = 16'h1234;
-
-		op = 4'h0;  // add
-		expected_result = 16'h1357;
-		expected_zero = 1'b0;
-		expected_carry = 1'b0;
-
-		#2
-		op = 4'h1;  // subtract
-		expected_result = 16'hEEEF;
-		expected_carry = 1'b1;
-		expected_zero = 1'b0;
-
-		#2
-		y = 16'h0123;
-		expected_result = 16'h0;
-		expected_zero = 1'b1;
-		expected_carry = 1'b0;
-
-		#2
-		y = 16'h1234;
-		op = 4'h2;  // multiply
-		expected_result = 16'hB11C;
-		expected_zero = 1'b0;
-		expected_carry = 1'b0;
+		file = $fopenr("tests/alu");
+
+		skip_comments(file);
+		while (!$feof(file)) begin
+			r = $fscanf(file, " 0x%x %3s 0x%x = 0x%x Z=%x C=%x\n", x, opstr, y, expected_result, expected_zero, expected_carry);
+
+			case (opstr)
+				"+" : op = 0;
+				"-" : op = 1;
+				"*" : op = 2;
+				"/" : op = 3;
+				"&" : op = 4;
+				"|" : op = 5;
+				"^" : op = 6;
+				default : op = 0;
+			endcase
+
+			#2
+			if (result != expected_result || zero != expected_zero || carry != expected_carry) begin
+				$display("TEST FAILED: 0x%04x %3s 0x%04x = 0x%04x Z=%x C=%x (expected 0x%04x Z=%x C=%x)", x, opstr, y, result, zero, carry, expected_result, expected_zero, expected_carry);
+			end
+			skip_comments(file);
+		end
 
 		#2
-		x = 16'h3E58;
-		y = 16'h0078;
-		op = 4'h3;  // divide
-		expected_result = 16'h0085;
-
-		#2
-		x = 16'hAF74;
-		y = 16'h7CC7;
-		op = 4'h4;  // and
-		expected_result = 16'h2C44;
-
-		#2
-		op = 4'h5;  // or
-		expected_result = 16'hFFF7;
-
-		#2
-		op = 4'h6;  // xor
-		expected_result = 16'hD3B3;
-
-		#5
+		$fclose(file);
 		$finish;
 	end
 
diff --git a/testbench.vh b/testbench.vh
new file mode 100644
index 0000000..9838164
--- /dev/null
+++ b/testbench.vh
@@ -0,0 +1,27 @@
+`ifndef TESTBENCH_VH
+`define TESTBENCH_VH
+
+`define MAX_LINE_LENGTH 128
+`define EOF 32'hFFFF_FFFF
+
+task skip_comments(input integer file);
+	integer c, r, quit;
+	reg [8*`MAX_LINE_LENGTH:0] line;
+
+	quit = 0;
+	while (quit == 0) begin
+		c = $fgetc(file);
+		if (c == `EOF) begin
+			quit = 1;
+		end else if (c == "#") begin
+			r = $fgets(line, file);
+		end else if (c != "\n") begin
+			r = $ungetc(c, file);
+			quit = 1;
+		end
+	end
+endtask
+
+`endif
+
+// vim: syntax=verilog
diff --git a/tests/alu b/tests/alu
new file mode 100644
index 0000000..7496359
--- /dev/null
+++ b/tests/alu
@@ -0,0 +1,19 @@
+# X op Y = RESULT ZERO CARRY
+#
+# Operations:
+#  +   : add
+#  -   : subtract
+#  *   : multiply
+#  /   : divide
+#  &   : and
+#  |   : or
+#  ^   : xor
+
+0x0123 + 0x1234 = 0x1357 Z=0 C=0
+0x0123 - 0x1234 = 0xeeef Z=0 C=1
+0x0123 - 0x0123 = 0x0000 Z=1 C=0
+0x0123 * 0x1234 = 0xb11c Z=0 C=0
+0x3e58 / 0x0078 = 0x0085 Z=0 C=0
+0xaf74 & 0x7cc7 = 0x2c44 Z=0 C=0
+0xaf74 | 0x7cc7 = 0xfff7 Z=0 C=0
+0xaf74 ^ 0x7cc7 = 0xd3b3 Z=0 C=0
-- 
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