From 7a8184a7c5b1e15c8c3446feb3a927b0fc347242 Mon Sep 17 00:00:00 2001 From: Nick McKinney Date: Thu, 29 Dec 2016 15:56:51 -0600 Subject: add simplistic status register and associated debug lines --- alu_stage.v | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'alu_stage.v') diff --git a/alu_stage.v b/alu_stage.v index e070e4e..3761f25 100644 --- a/alu_stage.v +++ b/alu_stage.v @@ -22,8 +22,11 @@ module alu_stage ( output reg [32:0] control_signals_out, output reg [15:0] imm_out, - output reg [15:0] pc_out + output reg [15:0] pc_out, + + output [1:0] dbg_statusreg ); + reg [1:0] statusReg; // decode signals wire [3:0] aluOp_in; @@ -101,7 +104,10 @@ module alu_stage ( imm_out <= imm_in; memData_out <= aluResult; pc_out <= pc_in; + statusReg <= {aluZero, aluCarry}; // not quite right; should only happen for a few instructions end end + + assign dbg_statusreg = statusReg; endmodule -- cgit v1.2.3