From 735258adcb9a61bb7e60b4fe5d31fd5add1a0e13 Mon Sep 17 00:00:00 2001 From: Bobby Bingham Date: Sat, 7 Jan 2017 15:27:20 -0600 Subject: Make simulations in icarus verilog useful --- alu_tb.v | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'alu_tb.v') diff --git a/alu_tb.v b/alu_tb.v index de9fe37..6afafbc 100644 --- a/alu_tb.v +++ b/alu_tb.v @@ -12,6 +12,9 @@ module alu_tb (); reg expected_carry; initial begin + $dumpfile("alu_tb.vcd"); + $dumpvars(0, alu_tb); + x = 16'h0123; y = 16'h1234; @@ -60,7 +63,7 @@ module alu_tb (); expected_result = 16'hD3B3; #5 - $stop; + $finish; end alu alu_inst ( -- cgit v1.2.3