From 44e4cb4cc79b169c7dbbcbdaf9789cef2548a915 Mon Sep 17 00:00:00 2001 From: Nick McKinney Date: Thu, 29 Dec 2016 21:34:31 -0600 Subject: add containing SoC module, pull test program memory out of CPU --- fetch_stage.v | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) (limited to 'fetch_stage.v') diff --git a/fetch_stage.v b/fetch_stage.v index 749927b..8e78a54 100644 --- a/fetch_stage.v +++ b/fetch_stage.v @@ -1,14 +1,28 @@ module fetch_stage ( input clk, input en, - output reg ready, - + input [15:0] addr_in, + output mem_re, + output [15:0] mem_addr, + input [15:0] mem_data, output reg [15:0] instr_out, output reg [15:0] pc_out ); + assign mem_re = en; + + always @(posedge clk) begin + if(en) begin + instr_out <= mem_data; + pc_out <= addr_in; + end + end + + assign mem_addr = addr_in; + +/* always @(posedge clk) begin if(en) begin ready <= 1'b1; @@ -45,5 +59,6 @@ module fetch_stage ( ready <= 1'b0; end end +*/ endmodule -- cgit v1.2.3