From 735258adcb9a61bb7e60b4fe5d31fd5add1a0e13 Mon Sep 17 00:00:00 2001 From: Bobby Bingham Date: Sat, 7 Jan 2017 15:27:20 -0600 Subject: Make simulations in icarus verilog useful --- regFile_tb.v | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'regFile_tb.v') diff --git a/regFile_tb.v b/regFile_tb.v index 59c2edd..0df3e48 100644 --- a/regFile_tb.v +++ b/regFile_tb.v @@ -12,6 +12,9 @@ module regFile_tb (); wire [15:0] dataB; initial begin + $dumpfile("regFile_tb.vcd"); + $dumpvars(0, regFile_tb); + clk = 1'b0; regA = 3'h0; @@ -63,7 +66,7 @@ module regFile_tb (); we = 1'b0; #5 - $stop; + $finish; end always #1 clk = !clk; -- cgit v1.2.3