`include "testbench.vh"
`timescale 1 ns / 100 ps

module alu_tb ();
	reg [3:0] op;
	reg [15:0] x;
	reg [15:0] y;
	wire [15:0] result;
	reg [15:0] expected_result;
	wire zero;
	reg expected_zero;
	wire carry;
	reg expected_carry;

	reg [3*8:0] opstr;
	integer file, r;

	initial begin
		$dumpfile("alu_tb.vcd");
		$dumpvars(0, alu_tb);

		file = $fopenr("tests/alu");

		skip_comments(file);
		while (!$feof(file)) begin
			r = $fscanf(file, " 0x%x %3s 0x%x = 0x%x Z=%x C=%x\n", x, opstr, y, expected_result, expected_zero, expected_carry);

			case (opstr)
				"+" : op = 0;
				"-" : op = 1;
				"*" : op = 2;
				"/" : op = 3;
				"&" : op = 4;
				"|" : op = 5;
				"^" : op = 6;
				default : op = 0;
			endcase

			#2
			if (result != expected_result || zero != expected_zero || carry != expected_carry) begin
				$display("TEST FAILED: 0x%04x %3s 0x%04x = 0x%04x Z=%x C=%x (expected 0x%04x Z=%x C=%x)", x, opstr, y, result, zero, carry, expected_result, expected_zero, expected_carry);
			end
			skip_comments(file);
		end

		#2
		$fclose(file);
		$finish;
	end

	alu alu_inst (
		.op(op),
		.x(x),
		.y(y),
		.result(result),
		.zero(zero),
		.carry(carry)
	);
endmodule