diff options
| -rw-r--r-- | alu_stage.v | 6 | ||||
| -rw-r--r-- | ctrl_decode.v | 4 | ||||
| -rw-r--r-- | ctrl_encode.v | 4 | ||||
| -rw-r--r-- | decoder.v | 38 | ||||
| -rw-r--r-- | decoder_stage.v | 6 | ||||
| -rw-r--r-- | nqcpu.v | 6 |
6 files changed, 32 insertions, 32 deletions
diff --git a/alu_stage.v b/alu_stage.v index 0ab5265..e070e4e 100644 --- a/alu_stage.v +++ b/alu_stage.v @@ -2,7 +2,7 @@ module alu_stage ( input clk, input en, input [15:0] pc_in, - input [31:0] control_signals_in, + input [32:0] control_signals_in, input [15:0] imm_in, // register file @@ -20,7 +20,7 @@ module alu_stage ( input [15:0] memData_in, // read in from memory output reg [15:0] memData_out, // to write out to memory - output reg [31:0] control_signals_out, + output reg [32:0] control_signals_out, output reg [15:0] imm_out, output reg [15:0] pc_out ); @@ -40,7 +40,7 @@ module alu_stage ( wire memReadW_in; wire memWriteB_in; wire memWriteW_in; - wire [4:0] setRegCond_in; + wire [5:0] setRegCond_in; ctrl_decode ctrl_decode_inst ( .control_signals(control_signals_in), diff --git a/ctrl_decode.v b/ctrl_decode.v index cda670d..ede591f 100644 --- a/ctrl_decode.v +++ b/ctrl_decode.v @@ -1,5 +1,5 @@ module ctrl_decode ( - input [31:0] control_signals, + input [32:0] control_signals, output [3:0] aluOp, output [2:0] aluReg1, @@ -18,7 +18,7 @@ module ctrl_decode ( output memWriteB, output memWriteW, - output [4:0] setRegCond // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this} + output [5:0] setRegCond // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this} ); assign { diff --git a/ctrl_encode.v b/ctrl_encode.v index 6eb0635..d76f34f 100644 --- a/ctrl_encode.v +++ b/ctrl_encode.v @@ -16,9 +16,9 @@ module ctrl_encode ( input memWriteB, input memWriteW, - input [4:0] setRegCond, // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this} + input [5:0] setRegCond, // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this} - output [31:0] control_signals + output [32:0] control_signals ); assign control_signals = { @@ -18,7 +18,7 @@ module decoder ( output memWriteB, output memWriteW, - output [4:0] setRegCond, // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this} + output [5:0] setRegCond, // {should set when condition is true, Z condition, combiner, C condition}, condition = (00: must be 0, 01: must be 1, 1x: don't care) output [15:0] imm ); @@ -111,14 +111,14 @@ module decoder ( // b** // 0110 + [which] + 0 + [immediate offset] -// which: 000 eq (Z = 1, S = x) -// 001 ne (Z = 0, S = x) -// 010 gt (Z = 0, S = 0) -// 011 ge (Z = x, S = 0) -// 100 lt (Z = 0, S = 1) -// 101 le (Z = x, S = 1) +// which: 000 eq (Z = 1 and C = 0) +// 001 ne (Z = 0 and C = x) +// 010 gt (Z = 0 and C = 0) +// 011 ge (Z = 1 or C = 0) +// 100 lt (Z = 0 and C = 1) +// 101 le (Z = 1 or C = 1) // 110 ?? -// 111 always (Z = x, S = x) +// 111 always (Z = x, C = x) // jmp // 0111 + 00000 + [reg1] + 00000 @@ -172,14 +172,14 @@ module decoder ( // for instr_branch wire [2:0] branch_cond = instr[11:9]; wire [7:0] branch_offset = instr[7:0]; - wire [4:0] branch_set_cond = - branch_cond == 3'h0 ? 5'b10110 : // EQ - branch_cond == 3'h1 ? 5'b10100 : // NE - branch_cond == 3'h2 ? 5'b10000 : // GT - branch_cond == 3'h3 ? 5'b11000 : // GE - branch_cond == 3'h4 ? 5'b10001 : // LT - branch_cond == 3'h5 ? 5'b11001 : // LE - 5'b11100; + wire [5:0] branch_set_cond = + branch_cond == 3'h0 ? 6'b1_01_1_00 : // EQ + branch_cond == 3'h1 ? 6'b1_00_1_10 : // NE + branch_cond == 3'h2 ? 6'b1_00_1_00 : // GT + branch_cond == 3'h3 ? 6'b1_01_0_00 : // GE + branch_cond == 3'h4 ? 6'b1_00_1_01 : // LT + branch_cond == 3'h5 ? 6'b1_01_0_01 : // LE + 6'b1_10_0_10; assign aluOp = instr_math ? {1'b0, math_op} : @@ -228,10 +228,10 @@ module decoder ( assign memWriteW = instr_mov ? (mov_mem & (!mov_mem_read & mov_word)) : 1'b0; assign setRegCond = - instr_mov ? ((!mov_mem | mov_mem_read) ? 5'b11100 : 5'b00000) : + instr_mov ? ((!mov_mem | mov_mem_read) ? 6'b1_10_0_10 : 6'b000000) : instr_branch ? branch_set_cond : - instr_nop ? 5'b00000 : - 5'b11100; + instr_nop ? 6'b000000 : + 6'b1_10_0_10; assign imm = instr_notneg ? {15'b0, notneg_is_neg} : diff --git a/decoder_stage.v b/decoder_stage.v index aad5f56..4919cdc 100644 --- a/decoder_stage.v +++ b/decoder_stage.v @@ -5,7 +5,7 @@ module decoder_stage ( input [15:0] instr_in, input [15:0] pc_in, - output reg [31:0] control_signals_out, + output reg [32:0] control_signals_out, output reg [15:0] imm_out, output reg [15:0] pc_out ); @@ -24,7 +24,7 @@ module decoder_stage ( wire memReadW_next; wire memWriteB_next; wire memWriteW_next; - wire [4:0] setRegCond_next; + wire [5:0] setRegCond_next; wire [15:0] imm_next; decoder decoder_inst ( @@ -47,7 +47,7 @@ module decoder_stage ( .imm(imm_next) ); - wire [31:0] control_signals_next; + wire [32:0] control_signals_next; ctrl_encode encode_inst ( .aluOp(aluOp_next), @@ -19,7 +19,7 @@ module nqcpu ( output debugMemWriteB, output debugMemWriteW, - output [4:0] debugSetRegCond, // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this} + output [5:0] debugSetRegCond, // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this} output [15:0] dbg_r0, output [15:0] dbg_r1, @@ -58,7 +58,7 @@ module nqcpu ( end end - wire [31:0] ctrl_from_decoder; + wire [32:0] ctrl_from_decoder; wire [15:0] imm_from_decoder; wire [15:0] pc_from_decoder; @@ -103,7 +103,7 @@ module nqcpu ( .dbg_r7(dbg_r7) ); - wire [31:0] ctrl_from_alu; + wire [32:0] ctrl_from_alu; wire [15:0] imm_from_alu; wire [15:0] pc_from_alu; alu_stage alu_inst ( |