create super simple fetch stage

2 files changed, 35 insertions, 0 deletions

diff --git a/fetch_stage.v b/fetch_stage.v
new file mode 100644
index 0000000..03621c3
--- /dev/null
+++ b/fetch_stage.v
@@ -0,0 +1,34 @@
+module fetch_stage (
+	input clk,
+	input en,
+	output reg ready,
+	
+	input [15:0] addr_in,
+	
+	output reg [15:0] instr_out
+);
+
+	always @(posedge clk) begin
+		if(en) begin
+			ready <= 1'b1;
+			
+			// sample proggy:
+			case(addr_in[15:1])
+				15'h0: instr_out <= 16'b0000_000_1_000_000_10;	// xor r0,r0,r0
+				15'h1: instr_out <= 16'b0000_001_1_001_001_10;	// xor r1,r1,r1
+				15'h2: instr_out <= 16'b0101_000_0_00010010;		// mov rl0,$12
+				15'h3: instr_out <= 16'b0101_001_0_00110100;		// mov rl1,$34
+				15'h4: instr_out <= 16'b0000_010_0_000_001_00;	// add r2,r0,r1
+				15'h5: instr_out <= 16'b0000_011_0_001_000_01;	// sub r3,r1,r0
+				15'h6: instr_out <= 16'b0100_000_0_011_00100;	// mov r0,r3
+				15'h7: instr_out <= 16'b0000_100_1_100_100_10;	// xor r4,r4,r4
+				15'h8: instr_out <= 16'b0111_00000_100_00000;	// jmp r4
+				default: instr_out <= 16'b1000_000000000000;		// nop
+			endcase
+		end
+		else begin
+			ready <= 1'b0;
+		end
+	end
+
+endmodule
diff --git a/nqcpu.qsf b/nqcpu.qsf
index db8dcc5..a96e544 100644
--- a/nqcpu.qsf
+++ b/nqcpu.qsf
@@ -59,4 +59,5 @@ set_global_assignment -name VERILOG_FILE decoder_stage.v
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE fetch_stage.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file