Make simulations in icarus verilog useful

3 files changed, 12 insertions, 3 deletions

diff --git a/alu_tb.v b/alu_tb.v
index de9fe37..6afafbc 100644
--- a/alu_tb.v
+++ b/alu_tb.v
@@ -12,6 +12,9 @@ module alu_tb ();
 	reg expected_carry;
 
 	initial begin
+		$dumpfile("alu_tb.vcd");
+		$dumpvars(0, alu_tb);
+
 		x = 16'h0123;
 		y = 16'h1234;
 
@@ -60,7 +63,7 @@ module alu_tb ();
 		expected_result = 16'hD3B3;
 
 		#5
-		$stop;
+		$finish;
 	end
 
 	alu alu_inst (
diff --git a/regFile_tb.v b/regFile_tb.v
index 59c2edd..0df3e48 100644
--- a/regFile_tb.v
+++ b/regFile_tb.v
@@ -12,6 +12,9 @@ module regFile_tb ();
 	wire [15:0] dataB;
 
 	initial begin
+		$dumpfile("regFile_tb.vcd");
+		$dumpvars(0, regFile_tb);
+
 		clk = 1'b0;
 
 		regA = 3'h0;
@@ -63,7 +66,7 @@ module regFile_tb ();
 		we = 1'b0;
 
 		#5
-		$stop;
+		$finish;
 	end
 
 	always #1 clk = !clk;
diff --git a/shifter_tb.v b/shifter_tb.v
index 278ac9a..f586d02 100644
--- a/shifter_tb.v
+++ b/shifter_tb.v
@@ -11,6 +11,9 @@ module shifter_tb ();
 	// xxxxxxxxxxxxxxxx1111101000001010xxxxxxxxxxxxxxxx
 
 	initial begin
+		$dumpfile("shifter_tb.vcd");
+		$dumpvars(0, shifter_tb);
+
 		v = 16'hFA0A;
 		by = 16'h0;
 		dir = 1'b0;
@@ -87,7 +90,7 @@ module shifter_tb ();
 		expected_result = 16'h0000;
 
 		#5
-		$stop;
+		$finish;
 	end
 
 	shifter shifter_inst (