summaryrefslogtreecommitdiff
path: root/ctrl_decode.v
diff options
context:
space:
mode:
authorNick McKinney <nick@kmonkey.net>2016-12-18 15:54:12 -0600
committerNick McKinney <nick@kmonkey.net>2016-12-18 15:54:12 -0600
commit9a8d8892361dcd16ad3801ce29e25516c8cd1019 (patch)
tree01f8cd27475fa5c9535b507d54eef7880f95a830 /ctrl_decode.v
parent603bee2b743f1a72222fd8586fa809555f08ea77 (diff)
Add ALU stage and hook it up. It sort of works.
Diffstat (limited to 'ctrl_decode.v')
-rw-r--r--ctrl_decode.v41
1 files changed, 41 insertions, 0 deletions
diff --git a/ctrl_decode.v b/ctrl_decode.v
new file mode 100644
index 0000000..cda670d
--- /dev/null
+++ b/ctrl_decode.v
@@ -0,0 +1,41 @@
+module ctrl_decode (
+ input [31:0] control_signals,
+
+ output [3:0] aluOp,
+ output [2:0] aluReg1,
+ output [2:0] aluReg2,
+ output [1:0] aluOpSource1, // ALU first operand: 0 = reg, 1 = memory read, 2 = imm8, 3 = PC
+ output [1:0] aluOpSource2, // ALU second operand: 0 = reg, 1 = ~reg, 2 = PC, 3 = ???
+ output aluDest, // 0 = reg, 1 = PC
+
+ output [2:0] regDest,
+ output regSetH,
+ output regSetL,
+
+ output [2:0] regAddr,
+ output memReadB,
+ output memReadW,
+ output memWriteB,
+ output memWriteW,
+
+ output [4:0] setRegCond // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this}
+);
+
+ assign {
+ aluOp,
+ aluReg1,
+ aluReg2,
+ aluOpSource1,
+ aluOpSource2,
+ aluDest,
+ regDest,
+ regSetH,
+ regSetL,
+ regAddr,
+ memReadB,
+ memReadW,
+ memWriteB,
+ memWriteW,
+ setRegCond
+ } = control_signals;
+endmodule