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author | Nick McKinney <nick@kmonkey.net> | 2016-12-18 15:54:12 -0600 |
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committer | Nick McKinney <nick@kmonkey.net> | 2016-12-18 15:54:12 -0600 |
commit | 9a8d8892361dcd16ad3801ce29e25516c8cd1019 (patch) | |
tree | 01f8cd27475fa5c9535b507d54eef7880f95a830 /ctrl_encode.v | |
parent | 603bee2b743f1a72222fd8586fa809555f08ea77 (diff) |
Add ALU stage and hook it up. It sort of works.
Diffstat (limited to 'ctrl_encode.v')
-rw-r--r-- | ctrl_encode.v | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/ctrl_encode.v b/ctrl_encode.v new file mode 100644 index 0000000..6eb0635 --- /dev/null +++ b/ctrl_encode.v @@ -0,0 +1,41 @@ +module ctrl_encode ( + input [3:0] aluOp, + input [2:0] aluReg1, + input [2:0] aluReg2, + input [1:0] aluOpSource1, // ALU first operand: 0 = reg, 1 = memory read, 2 = imm8, 3 = PC + input [1:0] aluOpSource2, // ALU second operand: 0 = reg, 1 = ~reg, 2 = PC, 3 = ??? + input aluDest, // 0 = reg, 1 = PC + + input [2:0] regDest, + input regSetH, + input regSetL, + + input [2:0] regAddr, + input memReadB, + input memReadW, + input memWriteB, + input memWriteW, + + input [4:0] setRegCond, // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this} + + output [31:0] control_signals +); + + assign control_signals = { + aluOp, + aluReg1, + aluReg2, + aluOpSource1, + aluOpSource2, + aluDest, + regDest, + regSetH, + regSetL, + regAddr, + memReadB, + memReadW, + memWriteB, + memWriteW, + setRegCond + }; +endmodule |