diff options
| -rw-r--r-- | control_unit.v | 36 | ||||
| -rw-r--r-- | nqcpu.qsf | 1 | ||||
| -rw-r--r-- | nqcpu.v | 27 |
3 files changed, 59 insertions, 5 deletions
diff --git a/control_unit.v b/control_unit.v new file mode 100644 index 0000000..00ebd4f --- /dev/null +++ b/control_unit.v @@ -0,0 +1,36 @@ +module control_unit ( + input clk, + + input fetch_ready, + + output fetch_en, + output decode_en, + output alu_en, + + output incr_pc, + + output [9:0] dbg_state +); + + reg [9:0] current_state; + + initial begin + current_state = 10'b1; + end + + assign fetch_en = current_state[0]; + assign decode_en = current_state[1]; + assign alu_en = current_state[2]; + + assign incr_pc = current_state[1]; + + always @(posedge clk) begin + case(current_state) + 10'b1: if(fetch_ready) current_state <= 10'b10; + 10'b10: current_state <= 10'b100; + 10'b100: current_state <= 10'b1; + endcase + end + + assign dbg_state = current_state; +endmodule @@ -64,4 +64,5 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name VERILOG_FILE alu_stage.v +set_global_assignment -name VERILOG_FILE control_unit.v set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file @@ -28,7 +28,8 @@ module nqcpu ( output [15:0] dbg_r4, output [15:0] dbg_r5, output [15:0] dbg_r6, - output [15:0] dbg_r7 + output [15:0] dbg_r7, + output [9:0] dbg_state ); reg [15:0] pc; @@ -37,12 +38,14 @@ module nqcpu ( pc = 16'h0; end + wire fetch_en, decode_en, alu_en, incr_pc; + wire fetch_ready; wire [15:0] fetched_instr; wire [15:0] pc_from_fetch; fetch_stage fetch_inst ( .clk(clk), - .en(1'b1), + .en(fetch_en), .addr_in(pc), .ready(fetch_ready), .instr_out(fetched_instr), @@ -50,7 +53,7 @@ module nqcpu ( ); always @(posedge clk) begin - if(fetch_ready) begin + if(incr_pc) begin pc <= pc + 16'h2; end end @@ -61,7 +64,7 @@ module nqcpu ( decoder_stage decoder_inst ( .clk(clk), - .en(fetch_ready), + .en(decode_en), .instr_in(fetched_instr), .pc_in(pc_from_fetch), .control_signals_out(ctrl_from_decoder), @@ -105,7 +108,7 @@ module nqcpu ( wire [15:0] pc_from_alu; alu_stage alu_inst ( .clk(clk), - .en(1'b1), + .en(alu_en), .pc_in(pc_from_decoder), .control_signals_in(ctrl_from_decoder), .imm_in(imm_from_decoder), @@ -130,6 +133,20 @@ module nqcpu ( .pc_out(pc_from_alu) ); + control_unit control_unit_inst ( + .clk(clk), + + .fetch_ready(fetch_ready), + + .fetch_en(fetch_en), + .decode_en(decode_en), + .alu_en(alu_en), + + .incr_pc(incr_pc), + + .dbg_state(dbg_state) + ); + ctrl_decode debug_decode ( .control_signals(ctrl_from_alu), |