diff options
Diffstat (limited to 'alu_stage.v')
| -rw-r--r-- | alu_stage.v | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/alu_stage.v b/alu_stage.v index b178cad..92c8246 100644 --- a/alu_stage.v +++ b/alu_stage.v @@ -2,7 +2,7 @@ module alu_stage ( input clk, input en, input [15:0] pc_in, - input [32:0] control_signals_in, + input [34:0] control_signals_in, input [15:0] imm_in, // register file @@ -24,7 +24,7 @@ module alu_stage ( output setPC, output [15:0] setPCValue, - output reg [32:0] control_signals_out, + output reg [34:0] control_signals_out, output reg [15:0] imm_out, output reg [15:0] pc_out, @@ -39,6 +39,8 @@ module alu_stage ( wire [1:0] aluOpSource1_in; wire [1:0] aluOpSource2_in; wire aluDest_in; + wire [1:0] aluCarrySource; + wire aluCarry_in; wire [2:0] regDest_in; wire regSetH_in; wire regSetL_in; @@ -58,6 +60,7 @@ module alu_stage ( .aluOpSource1(aluOpSource1_in), // ALU first operand: 0 = reg, 1 = memory read, 2 = imm8, 3 = PC .aluOpSource2(aluOpSource2_in), // ALU second operand: 0 = reg, 1 = ~reg, 2 = PC, 3 = ??? .aluDest(aluDest_in), // 0 = reg, 1 = PC + .aluCarrySource(aluCarrySource), // ALU carry input source: 0 = zero, 1 = one, 2 = carry flag, 3 = inverted carry flag .regDest(regDest_in), .regSetH(regSetH_in), @@ -83,12 +86,15 @@ module alu_stage ( aluOpSource1_in == 2'h0 ? rf_dataB : aluOpSource1_in == 2'h1 ? ~rf_dataIn : pc_in; + assign aluCarry_in = aluCarrySource[0] ^ (aluCarrySource[1] & statusReg[0]); + wire [15:0] aluResult; wire aluZero, aluCarry; alu alu_inst ( .op(aluOp_in), .x(aluSrc1), .y(aluSrc2), + .carry_in(aluCarry_in), .result(aluResult), .zero(aluZero), .carry(aluCarry) |