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-rw-r--r--decoder.v16
1 files changed, 8 insertions, 8 deletions
diff --git a/decoder.v b/decoder.v
index 38519f2..d6a1e02 100644
--- a/decoder.v
+++ b/decoder.v
@@ -1,6 +1,6 @@
module decoder (
input [15:0] instr,
-
+
output [3:0] aluOp,
output [2:0] aluReg1,
output [2:0] aluReg2,
@@ -11,15 +11,15 @@ module decoder (
output [2:0] regDest,
output regSetH,
output regSetL,
-
+
output [2:0] regAddr,
output memReadB,
output memReadW,
output memWriteB,
output memWriteW,
-
+
output [5:0] setRegCond, // {should set when condition is true, Z condition, combiner, C condition}, condition = (00: must be 0, 01: must be 1, 1x: don't care)
-
+
output [15:0] imm
);
@@ -143,14 +143,14 @@ module decoder (
which_instr == 4'h4 ? 10'b0000100000 :
which_instr == 4'h5 ? 10'b0000010000 :
which_instr == 4'h6 ? 10'b0000001000 :
- which_instr == 4'h7 ? 10'b0000000100 :
+ which_instr == 4'h7 ? 10'b0000000100 :
which_instr == 4'h8 ? 10'b0000000010 : 10'b0000000001;
// src/dest registers
wire [2:0] reg0 = instr[11:9];
wire [2:0] reg1 = instr[7:5];
wire [2:0] reg2 = instr[4:2];
-
+
wire [7:0] imm_param = instr[7:0];
wire [15:0] ext_imm_param = {{8{instr[7]}}, instr[7:0]}; // sign-extended immediate parameter
@@ -215,7 +215,7 @@ module decoder (
1'b0;
assign regDest = reg0;
-
+
assign regSetH =
instr_mov ? (mov_word | mov_dest_byte_high) :
instr_movimm ? movimm_high :
@@ -231,7 +231,7 @@ module decoder (
assign memReadW = instr_mov ? (mov_mem & (mov_mem_read & mov_word)) : 1'b0;
assign memWriteB = instr_mov ? (mov_mem & (!mov_mem_read & !mov_word)) : 1'b0;
assign memWriteW = instr_mov ? (mov_mem & (!mov_mem_read & mov_word)) : 1'b0;
-
+
assign setRegCond =
instr_mov ? ((!mov_mem | mov_mem_read) ? 6'b1_10_0_10 : 6'b000000) :
instr_branch ? branch_set_cond :