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* add simplistic status register and associated debug linesNick McKinney2016-12-292-3/+13
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* widen register set control signal, fix bugs with conditional sets related to ↵Nick McKinney2016-12-296-32/+32
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* add simple control unitNick McKinney2016-12-183-5/+59
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* Add ALU stage and hook it up. It sort of works.Nick McKinney2016-12-189-53/+429
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* create super simple fetch stageNick McKinney2016-12-082-0/+35
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* create decoder stageNick McKinney2016-12-082-1/+88
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* finish decoder v1Nick McKinney2016-12-083-21/+175
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* initial commitNick McKinney2016-12-0110-0/+601