1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
|
module decoder_stage (
input clk,
input en,
input [15:0] instr_in,
input [15:0] pc_in,
output reg [31:0] control_signals_out,
output reg [15:0] imm_out,
output reg [15:0] pc_out
);
wire [3:0] aluOp_next;
wire [2:0] aluReg1_next;
wire [2:0] aluReg2_next;
wire [1:0] aluOpSource1_next;
wire [1:0] aluOpSource2_next;
wire aluDest_next;
wire [2:0] regDest_next;
wire regSetH_next;
wire regSetL_next;
wire [2:0] regAddr_next;
wire memReadB_next;
wire memReadW_next;
wire memWriteB_next;
wire memWriteW_next;
wire [4:0] setRegCond_next;
wire [15:0] imm_next;
decoder decoder_inst (
.instr(instr_in),
.aluOp(aluOp_next),
.aluReg1(aluReg1_next),
.aluReg2(aluReg2_next),
.aluOpSource1(aluOpSource1_next),
.aluOpSource2(aluOpSource2_next),
.aluDest(aluDest_next),
.regDest(regDest_next),
.regSetH(regSetH_next),
.regSetL(regSetL_next),
.regAddr(regAddr_next),
.memReadB(memReadB_next),
.memReadW(memReadW_next),
.memWriteB(memWriteB_next),
.memWriteW(memWriteW_next),
.setRegCond(setRegCond_next),
.imm(imm_next)
);
wire [31:0] control_signals_next;
ctrl_encode encode_inst (
.aluOp(aluOp_next),
.aluReg1(aluReg1_next),
.aluReg2(aluReg2_next),
.aluOpSource1(aluOpSource1_next),
.aluOpSource2(aluOpSource2_next),
.aluDest(aluDest_next),
.regDest(regDest_next),
.regSetH(regSetH_next),
.regSetL(regSetL_next),
.regAddr(regAddr_next),
.memReadB(memReadB_next),
.memReadW(memReadW_next),
.memWriteB(memWriteB_next),
.memWriteW(memWriteW_next),
.setRegCond(setRegCond_next),
.control_signals(control_signals_next)
);
always @(posedge clk) begin
if(en) begin
control_signals_out <= control_signals_next;
imm_out <= imm_next;
pc_out <= pc_in;
end
end
endmodule
|
