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authorNick McKinney <nick@kmonkey.net>2016-12-29 15:54:36 -0600
committerNick McKinney <nick@kmonkey.net>2016-12-29 15:54:36 -0600
commit410a868f79165d6d2559bc8508ba496450fbe1ee (patch)
tree235c0362adbf0afd3fa0cda3170c752d360652bc /decoder_stage.v
parentd4cad6096651774485723551336bce1d08402b6e (diff)
widen register set control signal, fix bugs with conditional sets related to branching
Diffstat (limited to 'decoder_stage.v')
-rw-r--r--decoder_stage.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/decoder_stage.v b/decoder_stage.v
index aad5f56..4919cdc 100644
--- a/decoder_stage.v
+++ b/decoder_stage.v
@@ -5,7 +5,7 @@ module decoder_stage (
input [15:0] instr_in,
input [15:0] pc_in,
- output reg [31:0] control_signals_out,
+ output reg [32:0] control_signals_out,
output reg [15:0] imm_out,
output reg [15:0] pc_out
);
@@ -24,7 +24,7 @@ module decoder_stage (
wire memReadW_next;
wire memWriteB_next;
wire memWriteW_next;
- wire [4:0] setRegCond_next;
+ wire [5:0] setRegCond_next;
wire [15:0] imm_next;
decoder decoder_inst (
@@ -47,7 +47,7 @@ module decoder_stage (
.imm(imm_next)
);
- wire [31:0] control_signals_next;
+ wire [32:0] control_signals_next;
ctrl_encode encode_inst (
.aluOp(aluOp_next),