extract test rom into its own module

3 files changed, 53 insertions, 37 deletions

diff --git a/nqcpu.qsf b/nqcpu.qsf
index 59c802e..e5ab9d5 100644
--- a/nqcpu.qsf
+++ b/nqcpu.qsf
@@ -69,4 +69,5 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
 set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
 set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name VERILOG_FILE testROM.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/soc.v b/soc.v
index 3624279..292e8a1 100644
--- a/soc.v
+++ b/soc.v
@@ -73,43 +73,13 @@ module soc (
 		.dbg_statusreg(dbg_statusreg),
 	);
 
-	//-- debug ROM --
-	reg read_finished;
-	reg [15:0] romData;
-
-	assign needWait_i = re_o & !read_finished;
-	assign data_io = re_o ? romData : 16'hZZZZ;
-
-	initial begin
-		read_finished = 1'b0;
-		romData = 16'h0;
-	end
-
-	always @(posedge clk) begin
-		if(re_o) begin
-			read_finished <= 1'b1;
-
-			// sample proggy:
-			case(addr_o[15:1])
-				15'h0: romData <= 16'h0BB6;
-				15'h1: romData <= 16'h0102;
-				15'h2: romData <= 16'h0326;
-				15'h3: romData <= 16'h054A;
-				15'h4: romData <= 16'h5201;
-				15'h5: romData <= 16'h540A;
-				15'h6: romData <= 16'h0AA0;
-				15'h7: romData <= 16'h0004;
-				15'h8: romData <= 16'h0809;
-				15'h9: romData <= 16'h6AFA;
-				15'hA: romData <= 16'h6E00;
-				default: romData <= 16'b1111_000000000000;		// nop
-			endcase
-		end
-		else begin
-			read_finished <= 1'b0;
-		end
-	end
-	//---------------
+	testROM testROM_inst (
+		.clk(clk),
+		.needWait_o(needWait_i),
+		.addr_i(addr_o),
+		.re_i(re_o),
+		.data_io(data_io)
+	);
 
 	ctrl_decode debug_decode (
 		.control_signals(ctrl_from_decoder),
diff --git a/testROM.v b/testROM.v
new file mode 100644
index 0000000..e528f99
--- /dev/null
+++ b/testROM.v
@@ -0,0 +1,45 @@
+module testROM (
+	input clk,
+	
+	output needWait_o,
+	input [15:0] addr_i,
+	input re_i,
+	inout [15:0] data_io
+);
+
+	reg read_finished;
+	reg [15:0] romData;
+
+	assign needWait_o = re_i & !read_finished;
+	assign data_io = re_i ? romData : 16'hZZZZ;
+
+	initial begin
+		read_finished = 1'b0;
+		romData = 16'h0;
+	end
+
+	always @(posedge clk) begin
+		if(re_i) begin
+			read_finished <= 1'b1;
+
+			case(addr_i[15:1])
+				15'h0: romData <= 16'h0BB6;
+				15'h1: romData <= 16'h0102;
+				15'h2: romData <= 16'h0326;
+				15'h3: romData <= 16'h054A;
+				15'h4: romData <= 16'h5201;
+				15'h5: romData <= 16'h540A;
+				15'h6: romData <= 16'h0AA0;
+				15'h7: romData <= 16'h0004;
+				15'h8: romData <= 16'h0809;
+				15'h9: romData <= 16'h6AFA;
+				15'hA: romData <= 16'h6E00;
+				default: romData <= 16'b1111_000000000000;		// nop
+			endcase
+		end
+		else begin
+			read_finished <= 1'b0;
+		end
+	end
+
+endmodule