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author | Bobby Bingham <koorogi@koorogi.info> | 2017-01-07 15:26:04 -0600 |
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committer | Bobby Bingham <koorogi@koorogi.info> | 2017-01-08 22:02:28 -0600 |
commit | 7977ddd908a0af5ce4b176b05b31940cd7c8d50e (patch) | |
tree | 1b600d9e17a2de7c610b1304cf2914e7e35a3c7d /alu.v | |
parent | 209c6cf89e36ae3fdafa31543e77e5dd0047ece7 (diff) |
Remove trailing whitespace
Diffstat (limited to 'alu.v')
-rw-r--r-- | alu.v | 8 |
1 files changed, 4 insertions, 4 deletions
@@ -33,7 +33,7 @@ module alu ( wire [15:0] ored; wire [15:0] xored; wire [15:0] shifted; - + assign sum = x + y; assign diff = x - y; assign prod = x * y; @@ -41,7 +41,7 @@ module alu ( assign anded = x & y; assign ored = x | y; assign xored = x ^ y; - + shifter shifter_inst ( .v(x), .by(y), @@ -49,7 +49,7 @@ module alu ( .extend(op[1:0]), .result(shifted) ); - + assign result = op == 4'b0000 ? sum[15:0] : op == 4'b0001 ? diff[15:0] : @@ -60,7 +60,7 @@ module alu ( op == 4'b0110 ? xored : op == 4'b0111 ? x : shifted; - + assign zero = ~(|result); assign carry = op == 4'b0000 ? sum[16] : |