Remove trailing whitespace

8 files changed, 54 insertions, 54 deletions

diff --git a/alu.v b/alu.v
index 84a9159..5fbb8ba 100644
--- a/alu.v
+++ b/alu.v
@@ -33,7 +33,7 @@ module alu (
 	wire [15:0] ored;
 	wire [15:0] xored;
 	wire [15:0] shifted;
-	
+
 	assign sum = x + y;
 	assign diff = x - y;
 	assign prod = x * y;
@@ -41,7 +41,7 @@ module alu (
 	assign anded = x & y;
 	assign ored = x | y;
 	assign xored = x ^ y;
-	
+
 	shifter shifter_inst (
 		.v(x),
 		.by(y),
@@ -49,7 +49,7 @@ module alu (
 		.extend(op[1:0]),
 		.result(shifted)
 	);
-	
+
 	assign result =
 		op == 4'b0000 ? sum[15:0] :
 		op == 4'b0001 ? diff[15:0] :
@@ -60,7 +60,7 @@ module alu (
 		op == 4'b0110 ? xored :
 		op == 4'b0111 ? x :
 		shifted;
-	
+
 	assign zero = ~(|result);
 	assign carry =
 		op == 4'b0000 ? sum[16] :
diff --git a/alu_stage.v b/alu_stage.v
index 7bdbfe8..b178cad 100644
--- a/alu_stage.v
+++ b/alu_stage.v
@@ -15,15 +15,15 @@ module alu_stage (
 	output rf_lb,
 	input [15:0] rf_dataA,
 	input [15:0] rf_dataB,
-	
+
 	// memory interface
 	input [15:0] memData_in,    // read in from memory
 	output reg [15:0] memData_out,  // to write out to memory
-	
+
 	// setting PC
 	output setPC,
 	output [15:0] setPCValue,
-	
+
 	output reg [32:0] control_signals_out,
 	output reg [15:0] imm_out,
 	output reg [15:0] pc_out,
@@ -77,7 +77,7 @@ module alu_stage (
 		aluOpSource1_in == 2'h0 ? rf_dataA :
 		aluOpSource1_in == 2'h1 ? memData_in :
 		aluOpSource1_in == 2'h2 ? {imm_in} : pc_in;
-		
+
 	wire [15:0] aluSrc2;
 	assign aluSrc2 =
 		aluOpSource1_in == 2'h0 ? rf_dataB :
@@ -93,7 +93,7 @@ module alu_stage (
 		.zero(aluZero),
 		.carry(aluCarry)
 	);
-	
+
 	wire setRegZCond, setRegCCond, setSomeReg;
 	assign setRegZCond = setRegCond_in[4] | (setRegCond_in[3] == statusReg[1]);
 	assign setRegCCond = setRegCond_in[1] | (setRegCond_in[0] == statusReg[0]);
@@ -116,7 +116,7 @@ module alu_stage (
 
 	assign setPC = setSomeReg & aluDest_in;
 	assign setPCValue = aluResult;
-	
+
 	always @(posedge clk) begin
 		if(en) begin
 			control_signals_out <= control_signals_in;
@@ -126,7 +126,7 @@ module alu_stage (
 			statusReg <= {aluZero, aluCarry};  // not quite right; should only happen for a few instructions
 		end
 	end
-	
+
 	assign dbg_statusreg = statusReg;
 
 endmodule
diff --git a/alu_tb.v b/alu_tb.v
index dffe337..de9fe37 100644
--- a/alu_tb.v
+++ b/alu_tb.v
@@ -14,51 +14,51 @@ module alu_tb ();
 	initial begin
 		x = 16'h0123;
 		y = 16'h1234;
-		
+
 		op = 4'h0;  // add
 		expected_result = 16'h1357;
 		expected_zero = 1'b0;
 		expected_carry = 1'b0;
-		
+
 		#2
 		op = 4'h1;  // subtract
 		expected_result = 16'hEEEF;
 		expected_carry = 1'b1;
 		expected_zero = 1'b0;
-		
+
 		#2
 		y = 16'h0123;
 		expected_result = 16'h0;
 		expected_zero = 1'b1;
 		expected_carry = 1'b0;
-		
+
 		#2
 		y = 16'h1234;
 		op = 4'h2;  // multiply
 		expected_result = 16'hB11C;
 		expected_zero = 1'b0;
 		expected_carry = 1'b0;
-		
+
 		#2
 		x = 16'h3E58;
 		y = 16'h0078;
 		op = 4'h3;  // divide
 		expected_result = 16'h0085;
-		
+
 		#2
 		x = 16'hAF74;
 		y = 16'h7CC7;
 		op = 4'h4;  // and
 		expected_result = 16'h2C44;
-		
+
 		#2
 		op = 4'h5;  // or
 		expected_result = 16'hFFF7;
-		
+
 		#2
 		op = 4'h6;  // xor
 		expected_result = 16'hD3B3;
-		
+
 		#5
 		$stop;
 	end
diff --git a/decoder.v b/decoder.v
index 38519f2..d6a1e02 100644
--- a/decoder.v
+++ b/decoder.v
@@ -1,6 +1,6 @@
 module decoder (
 	input [15:0] instr,
-	
+
 	output [3:0] aluOp,
 	output [2:0] aluReg1,
 	output [2:0] aluReg2,
@@ -11,15 +11,15 @@ module decoder (
 	output [2:0] regDest,
 	output regSetH,
 	output regSetL,
-	
+
 	output [2:0] regAddr,
 	output memReadB,
 	output memReadW,
 	output memWriteB,
 	output memWriteW,
-	
+
 	output [5:0] setRegCond,   // {should set when condition is true, Z condition, combiner, C condition}, condition = (00: must be 0, 01: must be 1, 1x: don't care)
-	
+
 	output [15:0] imm
 );
 
@@ -143,14 +143,14 @@ module decoder (
 		which_instr == 4'h4 ? 10'b0000100000 :
 		which_instr == 4'h5 ? 10'b0000010000 :
 		which_instr == 4'h6 ? 10'b0000001000 :
-		which_instr == 4'h7 ? 10'b0000000100 : 
+		which_instr == 4'h7 ? 10'b0000000100 :
 		which_instr == 4'h8 ? 10'b0000000010 : 10'b0000000001;
 
 	// src/dest registers
 	wire [2:0] reg0 = instr[11:9];
 	wire [2:0] reg1 = instr[7:5];
 	wire [2:0] reg2 = instr[4:2];
-	
+
 	wire [7:0] imm_param = instr[7:0];
 	wire [15:0] ext_imm_param = {{8{instr[7]}}, instr[7:0]};  // sign-extended immediate parameter
 
@@ -215,7 +215,7 @@ module decoder (
 			1'b0;
 
 	assign regDest = reg0;
-	
+
 	assign regSetH =
 		instr_mov ? (mov_word | mov_dest_byte_high) :
 		instr_movimm ? movimm_high :
@@ -231,7 +231,7 @@ module decoder (
 	assign memReadW = instr_mov ? (mov_mem & (mov_mem_read & mov_word)) : 1'b0;
 	assign memWriteB = instr_mov ? (mov_mem & (!mov_mem_read & !mov_word)) : 1'b0;
 	assign memWriteW = instr_mov ? (mov_mem & (!mov_mem_read & mov_word)) : 1'b0;
-	
+
 	assign setRegCond =
 		instr_mov ? ((!mov_mem | mov_mem_read) ? 6'b1_10_0_10 : 6'b000000) :
 		instr_branch ? branch_set_cond :
diff --git a/decoder_stage.v b/decoder_stage.v
index 4919cdc..fcc7d60 100644
--- a/decoder_stage.v
+++ b/decoder_stage.v
@@ -4,7 +4,7 @@ module decoder_stage (
 
 	input [15:0] instr_in,
 	input [15:0] pc_in,
-	
+
 	output reg [32:0] control_signals_out,
 	output reg [15:0] imm_out,
 	output reg [15:0] pc_out
@@ -46,9 +46,9 @@ module decoder_stage (
 		.setRegCond(setRegCond_next),
 		.imm(imm_next)
 	);
-	
+
 	wire [32:0] control_signals_next;
-	
+
 	ctrl_encode encode_inst (
 		.aluOp(aluOp_next),
 		.aluReg1(aluReg1_next),
@@ -67,7 +67,7 @@ module decoder_stage (
 		.setRegCond(setRegCond_next),
 		.control_signals(control_signals_next)
 	);
-	
+
 	always @(posedge clk) begin
 		if(en) begin
 			control_signals_out <= control_signals_next;
diff --git a/regFile_tb.v b/regFile_tb.v
index 10839d0..59c2edd 100644
--- a/regFile_tb.v
+++ b/regFile_tb.v
@@ -10,10 +10,10 @@ module regFile_tb ();
 	reg we, hb, lb;
 	wire [15:0] dataA;
 	wire [15:0] dataB;
-	
+
 	initial begin
 		clk = 1'b0;
-		
+
 		regA = 3'h0;
 		regB = 3'h0;
 		regDest = 3'h0;
@@ -21,7 +21,7 @@ module regFile_tb ();
 		hb = 1'b0;
 		lb = 1'b0;
 		dataIn = 16'h0;
-		
+
 		#2
 		regA = 3'h1;
 		regDest = 3'h1;
@@ -29,26 +29,26 @@ module regFile_tb ();
 		we = 1'b1;
 		hb = 1'b1;
 		lb = 1'b1;
-		
+
 		#2
 		regB = 3'h1;
 		regA = 3'h2;
 		dataIn = 16'hBEEF;
 		lb = 1'b0;
-		
+
 		#2
 		lb = 1'b1;
-		
+
 		#2
 		regDest = 3'h2;
 		hb = 1'b0;
 		dataIn = 16'h9876;
-		
+
 		#2
 		hb = 1'b1;
 		lb = 1'b0;
 		dataIn = 16'h2345;
-		
+
 		#2
 		regB = 3'h7;
 		regDest = 3'h7;
@@ -56,18 +56,18 @@ module regFile_tb ();
 		hb = 1'b0;
 		we = 1'b1;
 		dataIn = 16'hFFCC;
-		
+
 		#2
 		lb = 1'b1;
 		hb = 1'b1;
 		we = 1'b0;
-		
+
 		#5
 		$stop;
 	end
-	
+
 	always #1 clk = !clk;
-	
+
 	regFile regFile_inst (
 		.clk(clk),
 		.regA(regA),
diff --git a/shifter_tb.v b/shifter_tb.v
index 7d28915..278ac9a 100644
--- a/shifter_tb.v
+++ b/shifter_tb.v
@@ -7,7 +7,7 @@ module shifter_tb ();
 	reg [1:0] extend;
 	wire [15:0] result;
 	reg [15:0] expected_result;
-	
+
 	// xxxxxxxxxxxxxxxx1111101000001010xxxxxxxxxxxxxxxx
 
 	initial begin
@@ -68,15 +68,15 @@ module shifter_tb ();
 		dir = 1'b0;
 		by = 16'hE;
 		expected_result = 16'h7FFF;
-		
+
 		#2
 		by = 16'h10;
 		expected_result = 16'hFFFF;
-		
+
 		#2
 		dir = 1'b1;
 		expected_result = 16'h0000;
-		
+
 		#2
 		dir = 1'b0;
 		by = 16'h1000;
@@ -85,11 +85,11 @@ module shifter_tb ();
 		#2
 		dir = 1'b1;
 		expected_result = 16'h0000;
-		
+
 		#5
 		$stop;
 	end
-	
+
 	shifter shifter_inst (
 		.v(v),
 		.by(by),
diff --git a/soc.v b/soc.v
index 292e8a1..20abd42 100644
--- a/soc.v
+++ b/soc.v
@@ -20,7 +20,7 @@ module soc (
 	output debugMemWriteW,
 
 	output [5:0] debugSetRegCond,
-	
+
 	output [15:0] dbg_r0,
 	output [15:0] dbg_r1,
 	output [15:0] dbg_r2,
@@ -30,13 +30,13 @@ module soc (
 	output [15:0] dbg_r6,
 	output [15:0] dbg_r7,
 	output [9:0] dbg_state,
-	
+
 	output dbg_setPC,
 	output [15:0] dbg_setPCValue,
-	
+
 	output [1:0] dbg_statusreg,
 	output dbg_needWait,
-	
+
 	output dbg_re_o,
 	output dbg_we_o,
 	output [15:0] dbg_addr_o,