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-rw-r--r--decoder_stage.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/decoder_stage.v b/decoder_stage.v
index 4919cdc..fcc7d60 100644
--- a/decoder_stage.v
+++ b/decoder_stage.v
@@ -4,7 +4,7 @@ module decoder_stage (
input [15:0] instr_in,
input [15:0] pc_in,
-
+
output reg [32:0] control_signals_out,
output reg [15:0] imm_out,
output reg [15:0] pc_out
@@ -46,9 +46,9 @@ module decoder_stage (
.setRegCond(setRegCond_next),
.imm(imm_next)
);
-
+
wire [32:0] control_signals_next;
-
+
ctrl_encode encode_inst (
.aluOp(aluOp_next),
.aluReg1(aluReg1_next),
@@ -67,7 +67,7 @@ module decoder_stage (
.setRegCond(setRegCond_next),
.control_signals(control_signals_next)
);
-
+
always @(posedge clk) begin
if(en) begin
control_signals_out <= control_signals_next;