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author | Bobby Bingham <koorogi@koorogi.info> | 2017-01-07 15:26:04 -0600 |
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committer | Bobby Bingham <koorogi@koorogi.info> | 2017-01-08 22:02:28 -0600 |
commit | 7977ddd908a0af5ce4b176b05b31940cd7c8d50e (patch) | |
tree | 1b600d9e17a2de7c610b1304cf2914e7e35a3c7d /decoder_stage.v | |
parent | 209c6cf89e36ae3fdafa31543e77e5dd0047ece7 (diff) |
Remove trailing whitespace
Diffstat (limited to 'decoder_stage.v')
-rw-r--r-- | decoder_stage.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/decoder_stage.v b/decoder_stage.v index 4919cdc..fcc7d60 100644 --- a/decoder_stage.v +++ b/decoder_stage.v @@ -4,7 +4,7 @@ module decoder_stage ( input [15:0] instr_in, input [15:0] pc_in, - + output reg [32:0] control_signals_out, output reg [15:0] imm_out, output reg [15:0] pc_out @@ -46,9 +46,9 @@ module decoder_stage ( .setRegCond(setRegCond_next), .imm(imm_next) ); - + wire [32:0] control_signals_next; - + ctrl_encode encode_inst ( .aluOp(aluOp_next), .aluReg1(aluReg1_next), @@ -67,7 +67,7 @@ module decoder_stage ( .setRegCond(setRegCond_next), .control_signals(control_signals_next) ); - + always @(posedge clk) begin if(en) begin control_signals_out <= control_signals_next; |