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-rw-r--r--fetch_stage.v19
-rw-r--r--nqcpu.qsf3
-rw-r--r--nqcpu.v74
-rw-r--r--soc.v142
4 files changed, 189 insertions, 49 deletions
diff --git a/fetch_stage.v b/fetch_stage.v
index 749927b..8e78a54 100644
--- a/fetch_stage.v
+++ b/fetch_stage.v
@@ -1,14 +1,28 @@
module fetch_stage (
input clk,
input en,
- output reg ready,
-
+
input [15:0] addr_in,
+ output mem_re,
+ output [15:0] mem_addr,
+ input [15:0] mem_data,
output reg [15:0] instr_out,
output reg [15:0] pc_out
);
+ assign mem_re = en;
+
+ always @(posedge clk) begin
+ if(en) begin
+ instr_out <= mem_data;
+ pc_out <= addr_in;
+ end
+ end
+
+ assign mem_addr = addr_in;
+
+/*
always @(posedge clk) begin
if(en) begin
ready <= 1'b1;
@@ -45,5 +59,6 @@ module fetch_stage (
ready <= 1'b0;
end
end
+*/
endmodule
diff --git a/nqcpu.qsf b/nqcpu.qsf
index 0550532..7204a1d 100644
--- a/nqcpu.qsf
+++ b/nqcpu.qsf
@@ -38,7 +38,7 @@
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
-set_global_assignment -name TOP_LEVEL_ENTITY nqcpu
+set_global_assignment -name TOP_LEVEL_ENTITY soc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:25:59 NOVEMBER 17, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
@@ -60,6 +60,7 @@ set_global_assignment -name VERILOG_FILE fetch_stage.v
set_global_assignment -name VERILOG_FILE ctrl_decode.v
set_global_assignment -name VERILOG_FILE ctrl_encode.v
set_global_assignment -name VERILOG_FILE nqcpu.v
+set_global_assignment -name VERILOG_FILE soc.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
diff --git a/nqcpu.v b/nqcpu.v
index ffb5f31..d920fa0 100644
--- a/nqcpu.v
+++ b/nqcpu.v
@@ -1,26 +1,15 @@
module nqcpu (
input clk,
- output [15:0] debugPC,
- output [3:0] debugAluOp,
- output [2:0] debugAluReg1,
- output [2:0] debugAluReg2,
- output [1:0] debugAluOpSource1, // ALU first operand: 0 = reg, 1 = memory read, 2 = imm8, 3 = PC
- output [1:0] debugAluOpSource2, // ALU second operand: 0 = reg, 1 = ~reg, 2 = PC, 3 = ???
- output debugAluDest, // 0 = reg, 1 = PC
-
- output [2:0] debugRegDest,
- output debugRegSetH,
- output debugRegSetL,
-
- output [2:0] debugRegAddr,
- output debugMemReadB,
- output debugMemReadW,
- output debugMemWriteB,
- output debugMemWriteW,
-
- output [5:0] debugSetRegCond, // {should set when condition is true, Z doesn't matter, S doesn't matter, Z must be this, S must be this}
+ input needWait_i,
+ output [15:0] addr_o,
+ output re_o, we_o,
+ inout [15:0] data_io,
+
+ output [15:0] debugPC,
+ output [9:0] dbg_state,
+ output [32:0] debugCtrl,
output [15:0] dbg_r0,
output [15:0] dbg_r1,
output [15:0] dbg_r2,
@@ -29,7 +18,6 @@ module nqcpu (
output [15:0] dbg_r5,
output [15:0] dbg_r6,
output [15:0] dbg_r7,
- output [9:0] dbg_state,
output dbg_setPC,
output [15:0] dbg_setPCValue,
@@ -37,6 +25,14 @@ module nqcpu (
output [1:0] dbg_statusreg
);
+ //-- handle data line tristate --
+ wire [15:0] data_i;
+ wire [15:0] data_o;
+
+ assign data_i = we_o ? 16'h0 : data_io;
+ assign data_io = we_o ? data_o : 16'hZZZZ;
+ //-------------------------------
+
reg [15:0] pc;
initial begin
@@ -46,17 +42,25 @@ module nqcpu (
wire fetch_en, decode_en, alu_en, incr_pc, setPC;
wire [15:0] setPCValue;
- wire fetch_ready;
+ wire fetch_re;
wire [15:0] fetched_instr;
wire [15:0] pc_from_fetch;
+ wire [15:0] fetch_addr;
fetch_stage fetch_inst (
.clk(clk),
.en(fetch_en),
+
.addr_in(pc),
- .ready(fetch_ready),
+ .mem_re(fetch_re),
+ .mem_addr(fetch_addr),
+ .mem_data(data_i),
.instr_out(fetched_instr),
.pc_out(pc_from_fetch)
);
+
+ assign re_o = fetch_re;
+ assign we_o = 1'b0;
+ assign addr_o = fetch_addr;
always @(posedge clk) begin
if(incr_pc) begin
@@ -150,7 +154,7 @@ module nqcpu (
control_unit control_unit_inst (
.clk(clk),
- .needWait(fetch_en & !fetch_ready),
+ .needWait(needWait_i),
.fetch_en(fetch_en),
.decode_en(decode_en),
@@ -161,29 +165,7 @@ module nqcpu (
.dbg_state(dbg_state)
);
- ctrl_decode debug_decode (
- .control_signals(ctrl_from_decoder),
-
- .aluOp(debugAluOp),
- .aluReg1(debugAluReg1),
- .aluReg2(debugAluReg2),
- .aluOpSource1(debugAluOpSource1),
- .aluOpSource2(debugAluOpSource2),
- .aluDest(debugAluDest),
-
- .regDest(debugRegDest),
- .regSetH(debugRegSetH),
- .regSetL(debugRegSetL),
-
- .regAddr(debugRegAddr),
- .memReadB(debugMemReadB),
- .memReadW(debugMemReadW),
- .memWriteB(debugMemWriteB),
- .memWriteW(debugMemWriteW),
-
- .setRegCond(debugSetRegCond)
- );
-
+ assign debugCtrl = ctrl_from_decoder;
assign debugPC = pc;
assign dbg_setPC = setPC;
assign dbg_setPCValue = setPCValue;
diff --git a/soc.v b/soc.v
new file mode 100644
index 0000000..3624279
--- /dev/null
+++ b/soc.v
@@ -0,0 +1,142 @@
+module soc (
+ input clk,
+
+ output [15:0] debugPC,
+ output [3:0] debugAluOp,
+ output [2:0] debugAluReg1,
+ output [2:0] debugAluReg2,
+ output [1:0] debugAluOpSource1,
+ output [1:0] debugAluOpSource2,
+ output debugAluDest,
+
+ output [2:0] debugRegDest,
+ output debugRegSetH,
+ output debugRegSetL,
+
+ output [2:0] debugRegAddr,
+ output debugMemReadB,
+ output debugMemReadW,
+ output debugMemWriteB,
+ output debugMemWriteW,
+
+ output [5:0] debugSetRegCond,
+
+ output [15:0] dbg_r0,
+ output [15:0] dbg_r1,
+ output [15:0] dbg_r2,
+ output [15:0] dbg_r3,
+ output [15:0] dbg_r4,
+ output [15:0] dbg_r5,
+ output [15:0] dbg_r6,
+ output [15:0] dbg_r7,
+ output [9:0] dbg_state,
+
+ output dbg_setPC,
+ output [15:0] dbg_setPCValue,
+
+ output [1:0] dbg_statusreg,
+ output dbg_needWait,
+
+ output dbg_re_o,
+ output dbg_we_o,
+ output [15:0] dbg_addr_o,
+ output [15:0] dbg_data_io
+);
+
+ wire needWait_i;
+ wire [15:0] addr_o;
+ wire re_o, we_o;
+ wire [15:0] data_io;
+ wire [32:0] ctrl_from_decoder;
+
+ nqcpu cpu_inst (
+ .clk(clk),
+ .needWait_i(needWait_i),
+ .addr_o(addr_o),
+ .re_o(re_o),
+ .we_o(we_o),
+ .data_io(data_io),
+
+ .debugCtrl(ctrl_from_decoder),
+ .debugPC(debugPC),
+ .dbg_r0(dbg_r0),
+ .dbg_r1(dbg_r1),
+ .dbg_r2(dbg_r2),
+ .dbg_r3(dbg_r3),
+ .dbg_r4(dbg_r4),
+ .dbg_r5(dbg_r5),
+ .dbg_r6(dbg_r6),
+ .dbg_r7(dbg_r7),
+ .dbg_state(dbg_state),
+ .dbg_setPC(dbg_setPC),
+ .dbg_setPCValue(dbg_setPCValue),
+ .dbg_statusreg(dbg_statusreg),
+ );
+
+ //-- debug ROM --
+ reg read_finished;
+ reg [15:0] romData;
+
+ assign needWait_i = re_o & !read_finished;
+ assign data_io = re_o ? romData : 16'hZZZZ;
+
+ initial begin
+ read_finished = 1'b0;
+ romData = 16'h0;
+ end
+
+ always @(posedge clk) begin
+ if(re_o) begin
+ read_finished <= 1'b1;
+
+ // sample proggy:
+ case(addr_o[15:1])
+ 15'h0: romData <= 16'h0BB6;
+ 15'h1: romData <= 16'h0102;
+ 15'h2: romData <= 16'h0326;
+ 15'h3: romData <= 16'h054A;
+ 15'h4: romData <= 16'h5201;
+ 15'h5: romData <= 16'h540A;
+ 15'h6: romData <= 16'h0AA0;
+ 15'h7: romData <= 16'h0004;
+ 15'h8: romData <= 16'h0809;
+ 15'h9: romData <= 16'h6AFA;
+ 15'hA: romData <= 16'h6E00;
+ default: romData <= 16'b1111_000000000000; // nop
+ endcase
+ end
+ else begin
+ read_finished <= 1'b0;
+ end
+ end
+ //---------------
+
+ ctrl_decode debug_decode (
+ .control_signals(ctrl_from_decoder),
+
+ .aluOp(debugAluOp),
+ .aluReg1(debugAluReg1),
+ .aluReg2(debugAluReg2),
+ .aluOpSource1(debugAluOpSource1),
+ .aluOpSource2(debugAluOpSource2),
+ .aluDest(debugAluDest),
+
+ .regDest(debugRegDest),
+ .regSetH(debugRegSetH),
+ .regSetL(debugRegSetL),
+
+ .regAddr(debugRegAddr),
+ .memReadB(debugMemReadB),
+ .memReadW(debugMemReadW),
+ .memWriteB(debugMemWriteB),
+ .memWriteW(debugMemWriteW),
+
+ .setRegCond(debugSetRegCond)
+ );
+
+ assign dbg_needWait = needWait_i;
+ assign dbg_re_o = re_o;
+ assign dbg_we_o = we_o;
+ assign dbg_addr_o = addr_o;
+ assign dbg_data_io = data_io;
+endmodule
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