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-rw-r--r--fetch_stage.v19
1 files changed, 17 insertions, 2 deletions
diff --git a/fetch_stage.v b/fetch_stage.v
index 749927b..8e78a54 100644
--- a/fetch_stage.v
+++ b/fetch_stage.v
@@ -1,14 +1,28 @@
module fetch_stage (
input clk,
input en,
- output reg ready,
-
+
input [15:0] addr_in,
+ output mem_re,
+ output [15:0] mem_addr,
+ input [15:0] mem_data,
output reg [15:0] instr_out,
output reg [15:0] pc_out
);
+ assign mem_re = en;
+
+ always @(posedge clk) begin
+ if(en) begin
+ instr_out <= mem_data;
+ pc_out <= addr_in;
+ end
+ end
+
+ assign mem_addr = addr_in;
+
+/*
always @(posedge clk) begin
if(en) begin
ready <= 1'b1;
@@ -45,5 +59,6 @@ module fetch_stage (
ready <= 1'b0;
end
end
+*/
endmodule