diff options
| -rw-r--r-- | alu_stage.v | 5 | ||||
| -rw-r--r-- | ctrl_decode.v | 2 | ||||
| -rw-r--r-- | ctrl_encode.v | 2 | ||||
| -rw-r--r-- | decoder.v | 2 |
4 files changed, 5 insertions, 6 deletions
diff --git a/alu_stage.v b/alu_stage.v index 92c8246..618cc89 100644 --- a/alu_stage.v +++ b/alu_stage.v @@ -58,7 +58,7 @@ module alu_stage ( .aluReg1(aluReg1_in), .aluReg2(aluReg2_in), .aluOpSource1(aluOpSource1_in), // ALU first operand: 0 = reg, 1 = memory read, 2 = imm8, 3 = PC - .aluOpSource2(aluOpSource2_in), // ALU second operand: 0 = reg, 1 = ~reg, 2 = PC, 3 = ??? + .aluOpSource2(aluOpSource2_in), // ALU second operand: 0 = reg, 1 = ???, 2 = PC, 3 = ??? .aluDest(aluDest_in), // 0 = reg, 1 = PC .aluCarrySource(aluCarrySource), // ALU carry input source: 0 = zero, 1 = one, 2 = carry flag, 3 = inverted carry flag @@ -83,8 +83,7 @@ module alu_stage ( wire [15:0] aluSrc2; assign aluSrc2 = - aluOpSource1_in == 2'h0 ? rf_dataB : - aluOpSource1_in == 2'h1 ? ~rf_dataIn : pc_in; + aluOpSource1_in == 2'h0 ? rf_dataB : pc_in; assign aluCarry_in = aluCarrySource[0] ^ (aluCarrySource[1] & statusReg[0]); diff --git a/ctrl_decode.v b/ctrl_decode.v index 86ecc97..ae861e0 100644 --- a/ctrl_decode.v +++ b/ctrl_decode.v @@ -5,7 +5,7 @@ module ctrl_decode ( output [2:0] aluReg1, output [2:0] aluReg2, output [1:0] aluOpSource1, // ALU first operand: 0 = reg, 1 = memory read, 2 = imm8, 3 = PC - output [1:0] aluOpSource2, // ALU second operand: 0 = reg, 1 = ~reg, 2 = PC, 3 = ??? + output [1:0] aluOpSource2, // ALU second operand: 0 = reg, 1 = ???, 2 = PC, 3 = ??? output aluDest, // 0 = reg, 1 = PC output [1:0] aluCarrySource, // ALU carry flag input source diff --git a/ctrl_encode.v b/ctrl_encode.v index 92ad3c6..be0e385 100644 --- a/ctrl_encode.v +++ b/ctrl_encode.v @@ -3,7 +3,7 @@ module ctrl_encode ( input [2:0] aluReg1, input [2:0] aluReg2, input [1:0] aluOpSource1, // ALU first operand: 0 = reg, 1 = memory read, 2 = imm8, 3 = PC - input [1:0] aluOpSource2, // ALU second operand: 0 = reg, 1 = ~reg, 2 = PC, 3 = ??? + input [1:0] aluOpSource2, // ALU second operand: 0 = reg, 1 = ???, 2 = PC, 3 = ??? input aluDest, // 0 = reg, 1 = PC input [1:0] aluCarrySource, // ALU carry flag input source @@ -5,7 +5,7 @@ module decoder ( output [2:0] aluReg1, output [2:0] aluReg2, output [1:0] aluOpSource1, // ALU first operand: 0 = reg, 1 = memory read, 2 = imm8, 3 = PC - output [1:0] aluOpSource2, // ALU second operand: 0 = reg, 1 = ~reg, 2 = PC, 3 = ??? + output [1:0] aluOpSource2, // ALU second operand: 0 = reg, 1 = ???, 2 = PC, 3 = ??? output aluDest, // 0 = reg, 1 = PC output [1:0] aluCarrySource, // ALU carry input source: 0 = zero, 1 = one, 2 = carry, 3 = ~carry |