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-rw-r--r--alu_stage.v5
1 files changed, 2 insertions, 3 deletions
diff --git a/alu_stage.v b/alu_stage.v
index 92c8246..618cc89 100644
--- a/alu_stage.v
+++ b/alu_stage.v
@@ -58,7 +58,7 @@ module alu_stage (
.aluReg1(aluReg1_in),
.aluReg2(aluReg2_in),
.aluOpSource1(aluOpSource1_in), // ALU first operand: 0 = reg, 1 = memory read, 2 = imm8, 3 = PC
- .aluOpSource2(aluOpSource2_in), // ALU second operand: 0 = reg, 1 = ~reg, 2 = PC, 3 = ???
+ .aluOpSource2(aluOpSource2_in), // ALU second operand: 0 = reg, 1 = ???, 2 = PC, 3 = ???
.aluDest(aluDest_in), // 0 = reg, 1 = PC
.aluCarrySource(aluCarrySource), // ALU carry input source: 0 = zero, 1 = one, 2 = carry flag, 3 = inverted carry flag
@@ -83,8 +83,7 @@ module alu_stage (
wire [15:0] aluSrc2;
assign aluSrc2 =
- aluOpSource1_in == 2'h0 ? rf_dataB :
- aluOpSource1_in == 2'h1 ? ~rf_dataIn : pc_in;
+ aluOpSource1_in == 2'h0 ? rf_dataB : pc_in;
assign aluCarry_in = aluCarrySource[0] ^ (aluCarrySource[1] & statusReg[0]);