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-rw-r--r--Makefile12
1 files changed, 11 insertions, 1 deletions
diff --git a/Makefile b/Makefile
index dca5e74..ed56a85 100644
--- a/Makefile
+++ b/Makefile
@@ -4,7 +4,11 @@ IVFLAGS := -g2005-sv
SIM_SRCS := $(wildcard *_tb.v)
SIMS := $(addprefix sims/,$(SIM_SRCS:.v=.sim))
WAVES := $(addprefix waves/,$(SIM_SRCS:.v=.vcd))
-DIRS := sims waves
+
+SYNTH_SRCS := $(filter-out %_tb.v,$(wildcard *.v))
+SYNTH_ICE40 := $(addprefix ice40/,$(SYNTH_SRCS:.v=.blif))
+
+DIRS := sims waves ice40
DEPS = $(sort $(1) $(foreach d,$(1),$(DEPS-$(d))))
DEPS-alu := $(call DEPS,shifter)
@@ -17,6 +21,8 @@ all: simulate
simulate: $(WAVES)
+synth-ice40: $(SYNTH_ICE40)
+
clean:
rm -rf $(DIRS)
@@ -28,6 +34,10 @@ waves/%.vcd: sims/%.sim | waves
.SECONDEXPANSION:
pc := %
+
+ice40/%.blif: %.v $$(patsubst $$(pc),$$(pc).v,$$(DEPS-$$*)) | ice40
+ yosys $(foreach v,$^,-p "read_verilog $v") -p "synth_ice40 -blif $@" | sed -e "1,/Printing statistics/d" -e "/Executing CHECK/,$$ d" | tee ice40/$*.size
+
sims/%_tb.sim: %_tb.v %.v testbench.vh $$(patsubst $$(pc),$$(pc).v,$$(DEPS-$$*)) | sims
$(IV) $(IVFLAGS) -o $@ $(filter-out %.vh,$^)