1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
|
IV := iverilog
IVFLAGS := -g2005-sv
SIM_SRCS := $(wildcard *_tb.v)
SIMS := $(addprefix sims/,$(SIM_SRCS:.v=.sim))
WAVES := $(addprefix waves/,$(SIM_SRCS:.v=.vcd))
SYNTH_SRCS := $(filter-out %_tb.v,$(wildcard *.v))
SYNTH_ICE40 := $(addprefix ice40/,$(SYNTH_SRCS:.v=.blif))
DIRS := sims waves ice40
DEPS = $(sort $(1) $(foreach d,$(1),$(DEPS-$(d))))
DEPS-alu := $(call DEPS,shifter)
DEPS-alu_stage := $(call DEPS,alu ctrl_decode)
DEPS-decoder_stage := $(call DEPS,decoder ctrl_encode)
DEPS-nqcpu := $(call DEPS,fetch_stage decoder_stage regFile alu_stage control_unit)
DEPS-soc := $(call DEPS,nqcpu testROM ctrl_decode)
all: simulate
simulate: $(WAVES)
synth-ice40: $(SYNTH_ICE40)
clean:
rm -rf $(DIRS)
$(DIRS):
mkdir -p $@
waves/%.vcd: sims/%.sim | waves
vvp $<
.SECONDEXPANSION:
pc := %
ice40/%.blif: %.v $$(patsubst $$(pc),$$(pc).v,$$(DEPS-$$*)) | ice40
yosys $(foreach v,$^,-p "read_verilog $v") -p "synth_ice40 -blif $@" | sed -e "1,/Printing statistics/d" -e "/Executing CHECK/,$$ d" | tee ice40/$*.size
sims/%_tb.sim: %_tb.v %.v testbench.vh $$(patsubst $$(pc),$$(pc).v,$$(DEPS-$$*)) | sims
$(IV) $(IVFLAGS) -o $@ $(filter-out %.vh,$^)
.PHONY: all simulate clean
.SECONDARY:
|
