blob: 12b015bbfd80cb65a56d874a0ded8fd772b0e146 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
|
IV := iverilog
IVFLAGS := -g2005-sv
SIM_SRCS := $(wildcard *_tb.v)
SIMS := $(SIM_SRCS:.v=.sim)
WAVES := $(SIM_SRCS:.v=.vcd)
DEPS = $(sort $(1) $(foreach d,$(1),$(DEPS-$(d))))
DEPS-alu := $(call DEPS,shifter)
DEPS-alu_stage := $(call DEPS,alu ctrl_decode)
DEPS-decoder_stage := $(call DEPS,decoder ctrl_encode)
DEPS-nqcpu := $(call DEPS,fetch_stage decoder_stage regFile alu_stage control_unit)
DEPS-soc := $(call DEPS,nqcpu testROM ctrl_decode)
all: simulate
simulate: $(WAVES)
clean:
rm -f $(SIMS) $(WAVES)
%.vcd: %.sim
vvp $<
.SECONDEXPANSION:
pc := %
%_tb.sim: %_tb.v %.v $$(patsubst $$(pc),$$(pc).v,$$(DEPS-$$*))
$(IV) $(IVFLAGS) -o $@ $^
.PHONY: all simulate clean
.SECONDARY:
|
