Make simulations in icarus verilog useful

1 files changed, 4 insertions, 1 deletions

diff --git a/alu_tb.v b/alu_tb.v
index de9fe37..6afafbc 100644
--- a/alu_tb.v
+++ b/alu_tb.v
@@ -12,6 +12,9 @@ module alu_tb ();
 	reg expected_carry;
 
 	initial begin
+		$dumpfile("alu_tb.vcd");
+		$dumpvars(0, alu_tb);
+
 		x = 16'h0123;
 		y = 16'h1234;
 
@@ -60,7 +63,7 @@ module alu_tb ();
 		expected_result = 16'hD3B3;
 
 		#5
-		$stop;
+		$finish;
 	end
 
 	alu alu_inst (