extract test rom into its own module

1 files changed, 7 insertions, 37 deletions

diff --git a/soc.v b/soc.v
index 3624279..292e8a1 100644
--- a/soc.v
+++ b/soc.v
@@ -73,43 +73,13 @@ module soc (
 		.dbg_statusreg(dbg_statusreg),
 	);
 
-	//-- debug ROM --
-	reg read_finished;
-	reg [15:0] romData;
-
-	assign needWait_i = re_o & !read_finished;
-	assign data_io = re_o ? romData : 16'hZZZZ;
-
-	initial begin
-		read_finished = 1'b0;
-		romData = 16'h0;
-	end
-
-	always @(posedge clk) begin
-		if(re_o) begin
-			read_finished <= 1'b1;
-
-			// sample proggy:
-			case(addr_o[15:1])
-				15'h0: romData <= 16'h0BB6;
-				15'h1: romData <= 16'h0102;
-				15'h2: romData <= 16'h0326;
-				15'h3: romData <= 16'h054A;
-				15'h4: romData <= 16'h5201;
-				15'h5: romData <= 16'h540A;
-				15'h6: romData <= 16'h0AA0;
-				15'h7: romData <= 16'h0004;
-				15'h8: romData <= 16'h0809;
-				15'h9: romData <= 16'h6AFA;
-				15'hA: romData <= 16'h6E00;
-				default: romData <= 16'b1111_000000000000;		// nop
-			endcase
-		end
-		else begin
-			read_finished <= 1'b0;
-		end
-	end
-	//---------------
+	testROM testROM_inst (
+		.clk(clk),
+		.needWait_o(needWait_i),
+		.addr_i(addr_o),
+		.re_i(re_o),
+		.data_io(data_io)
+	);
 
 	ctrl_decode debug_decode (
 		.control_signals(ctrl_from_decoder),