| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Define macro to simplify dumping of waves | Bobby Bingham | 2017-01-08 | 4 | -6/+11 |
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| * | Move ALU test cases to external testcase file | Bobby Bingham | 2017-01-08 | 4 | -48/+76 |
| | | | | | | | | This makes is a little easier to create new ALU testcases and to quickly read and understand the existing testcases. Additionally, the test bench itself can now report when a test fails, rather than requiring inspection on the waveform (though the waveform is still available). | ||||
| * | Add makefile | Bobby Bingham | 2017-01-08 | 1 | -0/+31 |
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| * | Make simulations in icarus verilog useful | Bobby Bingham | 2017-01-08 | 3 | -3/+12 |
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| * | Remove extraneous comma causing syntax error | Bobby Bingham | 2017-01-08 | 1 | -1/+1 |
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| * | Remove trailing whitespace | Bobby Bingham | 2017-01-08 | 8 | -54/+54 |
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| * | extract test rom into its own module | Nick McKinney | 2016-12-29 | 3 | -37/+53 |
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| * | force the optimizer to try harder | Nick McKinney | 2016-12-29 | 1 | -0/+3 |
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| * | rearrange some lines in project file | Nick McKinney | 2016-12-29 | 1 | -2/+2 |
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| * | add containing SoC module, pull test program memory out of CPU | Nick McKinney | 2016-12-29 | 4 | -49/+189 |
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| * | add timing constraints file | Nick McKinney | 2016-12-29 | 1 | -0/+107 |
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| * | replace fetch_ready with a "wait needed" input line | Nick McKinney | 2016-12-29 | 2 | -7/+9 |
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| * | start a wish list for instructions to add in the future | Nick McKinney | 2016-12-29 | 1 | -0/+5 |
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| * | change debug program to one that adds the numbers from 1 through 10 with a loop | Nick McKinney | 2016-12-29 | 1 | -9/+21 |
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| * | watch control lines from decoder instead of ALU | Nick McKinney | 2016-12-29 | 1 | -1/+1 |
| | | | | | makes more sense in the simulator output | ||||
| * | support setting PC for branch and jump instructions | Nick McKinney | 2016-12-29 | 2 | -4/+34 |
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| * | add initial zero values for registers | Nick McKinney | 2016-12-29 | 1 | -0/+11 |
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| * | add simplistic status register and associated debug lines | Nick McKinney | 2016-12-29 | 2 | -3/+13 |
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| * | widen register set control signal, fix bugs with conditional sets related to ↵ | Nick McKinney | 2016-12-29 | 6 | -32/+32 |
| | | | | | branching | ||||
| * | add simple control unit | Nick McKinney | 2016-12-18 | 3 | -5/+59 |
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| * | Add ALU stage and hook it up. It sort of works. | Nick McKinney | 2016-12-18 | 9 | -53/+429 |
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| * | create super simple fetch stage | Nick McKinney | 2016-12-08 | 2 | -0/+35 |
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| * | create decoder stage | Nick McKinney | 2016-12-08 | 2 | -1/+88 |
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| * | finish decoder v1 | Nick McKinney | 2016-12-08 | 3 | -21/+175 |
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| * | initial commit | Nick McKinney | 2016-12-01 | 10 | -0/+601 |
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index : nqcpu | |
| a small 16-bit cpu |
| summaryrefslogtreecommitdiff |