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* Add makefileBobby Bingham2017-01-081-0/+31
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* Make simulations in icarus verilog usefulBobby Bingham2017-01-083-3/+12
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* Remove extraneous comma causing syntax errorBobby Bingham2017-01-081-1/+1
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* Remove trailing whitespaceBobby Bingham2017-01-088-54/+54
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* extract test rom into its own moduleNick McKinney2016-12-293-37/+53
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* force the optimizer to try harderNick McKinney2016-12-291-0/+3
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* rearrange some lines in project fileNick McKinney2016-12-291-2/+2
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* add containing SoC module, pull test program memory out of CPUNick McKinney2016-12-294-49/+189
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* add timing constraints fileNick McKinney2016-12-291-0/+107
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* replace fetch_ready with a "wait needed" input lineNick McKinney2016-12-292-7/+9
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* start a wish list for instructions to add in the futureNick McKinney2016-12-291-0/+5
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* change debug program to one that adds the numbers from 1 through 10 with a loopNick McKinney2016-12-291-9/+21
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* watch control lines from decoder instead of ALUNick McKinney2016-12-291-1/+1
| | | | makes more sense in the simulator output
* support setting PC for branch and jump instructionsNick McKinney2016-12-292-4/+34
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* add initial zero values for registersNick McKinney2016-12-291-0/+11
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* add simplistic status register and associated debug linesNick McKinney2016-12-292-3/+13
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* widen register set control signal, fix bugs with conditional sets related to ↵Nick McKinney2016-12-296-32/+32
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* add simple control unitNick McKinney2016-12-183-5/+59
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* Add ALU stage and hook it up. It sort of works.Nick McKinney2016-12-189-53/+429
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* create super simple fetch stageNick McKinney2016-12-082-0/+35
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* create decoder stageNick McKinney2016-12-082-1/+88
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* finish decoder v1Nick McKinney2016-12-083-21/+175
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* initial commitNick McKinney2016-12-0110-0/+601
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